There are many well-known techniques for encoding digital data for transmission or recording. One such popular technique is called Miller encoding, where digital ones and zeros are represented by transitions at different locations during a bit cell. A bit cell is the time interval occupied by each data bit. The placement of the transition within the bit cell conveys information regardless of the polarity of the transition, i.e., a high-to-low transition or a low-to-high transition. In Miller encoding, a one bit is encoded with a transition (from the previous state) at the middle of the bit cell. Consecutive zero bits are encoded by a transition at the beginning of each bit cell. Single, isolated zero bits are ignored, i.e., there are no transitions for single isolated zeros. Miller encoding permits regeneration of the clock signal from the Miller-encoded data signal; however, for proper decoding the clock signal must have a rate of twice the bit cell time. That is, two clock pulses must occur during each bit cell.
One disadvantage associated with Miller-encoding is that the encoded data does not have a regularly-repetitive transition edge for use in synchronizing a clock signal; that is, transitions may occur at one bit cell interval, one-and-one half bit cell intervals, or two bit cell intervals depending on the data pattern. The data is said to be "missing transitions" and hence it is not possible to employ a simple phase detector to compare the Miller-encoded data signals and the clock signal to synchronize them (i.e., to make the Miller-encoded data signal and the clock signal phase coherent). A phase detector looks at signal transitions or edges; with missing transitions for certain data patterns, the phase detector output would be erroneous.
One technique for synchronizing Miller-encoded data to a clock signal is disclosed in U.S. Pat. No. 4,124,778, entitled "Digital Frame Synchronizing Circuit." This patent discloses a phase-locked loop (including a phase detector and a voltage-controlled oscillator) to provide bit synchronization and clock signal regeneration. The well-known Miller encoding scheme is modified to provide a synchronization signal having a duration of three bit cells, thus generating a lower frequency signal than the Miller-encoding scheme. The phase-locked loop includes a feedback gate that is controlled by the synchronization signal. The feedback gate permits the clock signal from the voltage-controlled oscillator to be received as an input to the phase detector only when the synchronization signal is high. The phase detector compares the Miller-encoded signal and the clock signal to control the voltage-controlled oscillator so that a clock signal at twice the bit cell rate, which is necessary for decoding of the Miller-encoded data, is provided.